Physical Design Engineer (9 to 15 years)

A "Physical Design Engineer" with 9-15 years of experience is a senior-level position in semiconductor companies, responsible for designing and implementing the physical layout of integrated circuits (ICs) based on design specifications and constraints. The job description for this role typically includes the following responsibilities and qualifications:

Responsibilities:

1. Physical Design Flow: Lead and execute the physical design flow, including floorplanning, placement, routing, and timing closure, for complex IC designs using industry-standard tools and methodologies.
2. Floorplanning: Develop floorplans considering power grid, signal integrity, area constraints, and partitioning for optimal placement of IP blocks and sub-systems.
3. Placement and Routing: Perform top-level and block-level placement to achieve timing, area, and power targets, and execute detailed routing to meet design rules and performance requirements.
4. Clock Tree Synthesis: Design and optimize clock trees for synchronous designs, considering skew, jitter, and power considerations.
5. Power Planning and Analysis: Implement power grids, perform power analysis, and optimize power distribution to meet low-power design goals.
6. Timing Closure: Perform static timing analysis (STA), identify timing violations, and implement optimizations such as buffer insertion, slack redistribution, and gate sizing to achieve timing closure.
7. Physical Verification: Conduct physical verification checks, including design rule checks (DRC), layout versus schematic (LVS) checks, and electrical rule checks (ERC), and address violations to ensure tape-out readiness.
8. Collaboration: Work closely with front-end design teams, technology teams, and other stakeholders to understand design requirements, resolve design issues, and achieve design closure.
9. Documentation: Maintain documentation related to physical design specifications, constraints, methodologies, and implementation details for design reviews and tape-out documentation.

Qualifications:

1. Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
2. Experience: 9-15 years of experience in physical design of ICs, including expertise in leading-edge technology nodes and complex designs.
3. Tools and Methodologies: Proficiency in using industry-standard physical design tools such as Cadence Innovus, Synopsys ICC, Mentor Olympus, etc., and familiarity with design methodologies like hierarchical design, multi-voltage domain design, and low-power design techniques.
4. Timing Closure Skills: Strong understanding of timing closure methodologies, STA tools, and techniques for meeting timing requirements in high-performance designs.
5. Power Analysis: Experience with power analysis tools and techniques for power grid design, power optimization, and low-power design methodologies.
6. Physical Verification: Knowledge of physical verification tools and methodologies, including DRC, LVS, ERC, and familiarity with foundry-specific design rules and sign-off requirements.
7. Scripting and Automation: Proficiency in scripting languages like Tcl, Perl, or Python for automation of design tasks, tool flows, and design data analysis.
8. Communication and Leadership: Excellent communication skills and the ability to work effectively in cross-functional teams, mentor junior engineers, and lead physical design projects.

Overall, a Physical Design Engineer with 9-15 years of experience plays a crucial role in the successful implementation of IC designs, ensuring compliance with design rules, performance targets, and tape-out requirements.