Full Chip LVS lead

A "Full Chip LVS Lead" is a key role in semiconductor companies responsible for leading Layout vs. Schematic (LVS) verification activities for entire chip designs. The job description for this role typically includes the following responsibilities and qualifications:

Responsibilities:

1. LVS Verification Planning: Develop and execute comprehensive LVS verification plans for full chip designs to ensure layout accuracy and compliance with design specifications.
2. Team Leadership: Lead and manage a team of LVS verification engineers responsible for performing LVS checks and resolving discrepancies in layout and schematic representations.
3. Tool Selection and Setup: Evaluate, select, and set up LVS verification tools and flows, such as Cadence Assura, Mentor Calibre, Synopsys IC Validator, etc., for efficient and accurate verification.
4. LVS Debugging: Oversee and participate in debugging LVS violations, identifying root causes, and collaborating with design teams to resolve layout and schematic discrepancies.
5. Collaboration: Work closely with physical design teams, circuit designers, and other stakeholders to understand design intent, resolve LVS issues, and ensure layout correctness.
6. Methodology Development: Develop and implement best practices, methodologies, and automation scripts for streamlining LVS verification processes and improving productivity.
7. Documentation: Maintain documentation related to LVS verification plans, results, debug reports, and issues encountered during verification activities.

Qualifications:

1. Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
2. Experience: Several years of experience in LVS verification for complex full chip designs, including experience in a lead or senior role.
3. LVS Tools: Proficiency in using industry-standard LVS verification tools such as Cadence Assura, Mentor Calibre, Synopsys IC Validator, etc., and familiarity with LVS verification methodologies.
4. Scripting and Automation: Strong scripting skills in languages such as Tcl, Perl, or Python for developing automation scripts to enhance LVS verification efficiency and coverage.
5. Layout and Schematic Understanding: In-depth understanding of layout design principles, schematic representations, and LVS verification methodologies to ensure accurate verification results.
6. Debugging Skills: Excellent debugging and problem-solving skills, with the ability to analyze complex LVS violations and collaborate with design teams to resolve issues.
7. Communication and Leadership: Strong communication, teamwork, and leadership skills to lead LVS verification projects, collaborate with cross-functional teams, and mentor junior engineers.

Overall, a Full Chip LVS Lead plays a critical role in ensuring the accuracy and integrity of chip designs through comprehensive LVS verification, contributing to the development of high-quality semiconductor products.