Senior Engineer- HIG High Bandwidth Memory (Layout Design)
hyderabad, India
Full Time
Mid Level
As a Layout Design engineer, you will be working for intensive applications such as artificial intelligence and high-performance computing solution, High Bandwidth Memory. As a Layout Design Engineer you will be collaborating with peer teams crossing in a multiple projects-based environment.
Role and Responsibilities
• Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support.
• Perform layout verification like LVS/DRC/Antenna, quality check and support documentation.
• Responsible for on-time delivery of block-level layouts with acceptable quality.
• Demonstrate leadership qualities in planning, area/time estimation, scheduling, and execution to meet project schedule/milestones in multiple project environment.
• Ability to guide junior team-members in their execution of Sub block-level layouts & review critical items.
• Contribute to effective project-management.
• Effectively communicating with Global engineering teams to assure the success of layout project.
Qualification/Requirements
• 5 to 9 years' experience in analog/custom layout design in advanced CMOS process, in various technology nodes (Planar, FinFET )
• Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must.
• Should have hands on experience in creating layout of critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc.,
• Good understanding of Analog Layout fundamentals (e.g., Matching, Electro-migration, Latch-up, coupling, crosstalk, IR-drop, active and passive parasitic devices etc.)
• Understanding layout effects on the circuit such as speed, capacitance, power and area etc.,
• Ability to understand design constraints and implement high-quality layouts.
• Excellent problem-solving skills in physical verification of custom layout.
• Multiple Tape out support experience will be an added advantage.
• Excellent verbal and written communication skills.
Education
• BE or MTech in Electronic/VLSI Engineering
Role and Responsibilities
• Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support.
• Perform layout verification like LVS/DRC/Antenna, quality check and support documentation.
• Responsible for on-time delivery of block-level layouts with acceptable quality.
• Demonstrate leadership qualities in planning, area/time estimation, scheduling, and execution to meet project schedule/milestones in multiple project environment.
• Ability to guide junior team-members in their execution of Sub block-level layouts & review critical items.
• Contribute to effective project-management.
• Effectively communicating with Global engineering teams to assure the success of layout project.
Qualification/Requirements
• 5 to 9 years' experience in analog/custom layout design in advanced CMOS process, in various technology nodes (Planar, FinFET )
• Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must.
• Should have hands on experience in creating layout of critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc.,
• Good understanding of Analog Layout fundamentals (e.g., Matching, Electro-migration, Latch-up, coupling, crosstalk, IR-drop, active and passive parasitic devices etc.)
• Understanding layout effects on the circuit such as speed, capacitance, power and area etc.,
• Ability to understand design constraints and implement high-quality layouts.
• Excellent problem-solving skills in physical verification of custom layout.
• Multiple Tape out support experience will be an added advantage.
• Excellent verbal and written communication skills.
Education
• BE or MTech in Electronic/VLSI Engineering
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