Physical Design Engineer (15+ years)

A "Physical Design Engineer" with 15+ years of experience is a senior-level position in semiconductor companies, responsible for leading and executing physical design activities for complex integrated circuits (ICs) and System-on-Chip (SoC) designs. The job description for this role typically includes the following responsibilities and qualifications:

Responsibilities:

1. Physical Design Flow: Lead and execute the complete physical design flow, including floor planning, placement, clock tree synthesis (CTS), routing, timing closure, and physical verification.
2. Design Implementation: Implement high-performance and low-power designs while meeting area, power, and performance (PPA) targets.
3. Timing Closure: Perform timing analysis, optimization, and closure to meet timing constraints and achieve design goals.
4. Power Optimization: Implement power optimization techniques such as power gating, clock gating, and voltage scaling to achieve low-power design objectives.
5. Physical Verification: Perform physical verification tasks, including design rule checks (DRC), layout vs. schematic checks (LVS), electrical rule checks (ERC), and other sign-off checks.
6. Technology Nodes: Work with advanced technology nodes and process technologies to ensure optimal design implementation and performance.
7. Collaboration: Collaborate with front-end design teams, timing closure teams, synthesis teams, and other cross-functional teams to ensure successful tape-out of ICs and SoCs.
8. Methodology and Tool Development: Contribute to the development and improvement of physical design methodologies, flows, and automation scripts to enhance productivity and quality.

Qualifications:

1. Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
2. Experience: 15+ years of experience in physical design of complex ICs and SoCs, with hands-on experience in leading-edge technology nodes.
3. Tools: Proficiency in using industry-standard physical design tools such as Cadence Innovus, Synopsys ICC, Mentor Olympus-SoC, etc., and familiarity with EDA tools for timing analysis and physical verification.
4. Timing Closure: Expertise in timing closure techniques, static timing analysis (STA), clock domain crossing (CDC) analysis, and timing convergence methodologies.
5. Power Optimization: Experience with power optimization techniques, power grid design, power distribution network (PDN) analysis, and low-power design methodologies.
6. Physical Verification: Knowledge of physical verification methodologies, DRC/LVS/ERC checks, and sign-off criteria for tape-out readiness.
7. Scripting and Automation: Strong scripting skills in languages like Tcl, Perl, Python, or Shell scripting for automation of design tasks, flows, and tool interactions.
8. Problem-Solving: Excellent problem-solving skills, with the ability to analyze complex issues, debug physical design problems, and propose effective solutions.
9. Communication and Leadership: Strong communication, teamwork, and leadership skills to collaborate effectively with cross-functional teams, mentor junior engineers, and lead physical design projects.

Overall, a Physical Design Engineer with 15+ years of experience plays a crucial role in ensuring the successful implementation and tape-out of advanced ICs and SoCs, contributing to the development of high-performance and reliable semiconductor products